Thursday, November 8, 2018

Architecting an ASIC: Notes on VLSI Chip Design

"I am a quantum engineer, but on Sundays, I have principles."
- John Bell

Today VLSI capability allows to integrate multi-billion gates on a silicon chip. And therefore, architecting a (System-on)-Chip also needs to be a methodical process.

Questions to ask before starting with a SoC Chip-Design?[1]
  1. Power vs Performance: Is the chip designed to be power efficient or able to deliver performance?
  2. Is the design an embedded processor (that runs algorithms) or algorithms need to be running on the hardware?
  3. What kind of processor is necessary with what amount of local memory?
  4. Internal SRAM vs External DRAM (chip)?
  5. Local Storage vs External SSD/HDD storage?
  6. External (Communication) Interfaces - PCIe, FMC, SMA, Eth?
  7. Ethernet Connectivity/Ethernet Controller required?
  8. How many clocks would be required and what frequencies?
  9. What is going to be the reset scheme?
  10. Is internal caching required to improve performance (reduce latency)?
  11. Gate Count Budget, Power Budget, Pin budget?
  12. Is it going to be pad-limited or core-limited?
  13. Flexibility; Design Something modular (so that the core remains the same and external features can be modified for different market segments)?
  14. All in house vs using IPs?
  15. Can customizing standard IPs provide performance? (check with vendors for rights)
Architecture and Micro-architecture
Micro-architecture can be divided into three parts:
- Partitioning the Chip
- Data path within the Chip
- Control Functions

1. Partitioning the Chip: Break down the idea into easier-to-understand functionalities (Divide-and-Conquer).
2. Datapath Design: Do I need FIFOs, Multiplexers, Adders, Multipliers, ECC, CRC, Encoding/decoding, scrambling/encryption? Internal data-path size - 32-bit, 64bit, 128-bit?
3. Control Functions: Do I need state-machines? How many? Encoded State-Machines vs One-hot state machine? Full Handshake vs half-handshake in data transfer between different clock domains?

[For a good design, the above 3 should be followed in the same order as given above. Directly jumping into control logic doesn't help accelerate things, it makes it complicated.]

KISS and the 80-20 rule:
One of the referred strategies to digital design is KISS (Keep It Simple Stupid). 'Simplicity' refers to a design that is simple and meets all the functionality criteria. Further, simpler designs are easy to understand, debug and port.
Further, understanding trade-offs in a digital design is equally important. The 80-20 rules is a good approximation. Think of it like this: only 20% of your design will work 80% of the time and the rest, 80% of it would work only 20% of the times. In such as scenario, what would be the best configurations for a design and which sub-systems (functionalities) require more optimizations/improvements.

Understanding Errors:
hardware architectures are prone to errors timing mismatch in parallel lines, Metastability issues, etc. A hardware extension to handling these errors is a good idea but often these errors can be reported back to the software (which has the capabilities to handle these errors with more flexibility.)

Getting Started with HDL (VHDL/Verilog):
There are often many questions found throughout the internet inquiring what is the best way to get started and become proficient with one of the hardware description languages? The answer is quite simple, to be honest (and is expressed in more than one ways as answers to those questions.): Strengthen you digital design principles and practice coding the simple designs.

A good place to get started with this is:
I will make sure to form a Git Repository for the same and many more of such problems that would help get started with HDL.

As you progress, you figure the best design practices and what tools to use, on your own. I will dedicate a separate post on the best design practices I have figured till now.

[1] Advanced Chip Design: Practical Examples in Verilog by Kishore Mishra.