| Formal Verification primer
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Formal verification (abbr. as FV) is the use of tools that mathematically analyze the space of possible behaviors of a design, rather than computing results for particular values.

This means that FV tools will look a the full space of possible simulations (by using clever mathematical techniques) rather than trying out specific values. Today, FV is an essential element of the design and tapeout flow, specially in critial areas, that can help prevent dangerous bug escapes of potentially serious repurcussions (for example, Intel FDIV bug from early 1990s).

FV should be employed from the start of early development up through the post silicon debug process appropriately at every design phase to improve design throughput, increase the confidence in the design and reduce the time to market.

There are essentially many reasons to inculcate formal verification in your design flow. Some of them are as follow:

References:

  1. Eric Seligman, Tom Schubert, M V Achutha Kiran Kumar, Formal Verification: An Essential Toolkit for Modern VLSI Design, Morgan Kaufmann publications by Elsevier Inc. (2015).

Disclaimer:

A large part of the post are direct paraphrasing or direct quotations from the books and other online references. All credits are therefore attributed to the original authors. This post serves as a means to organize and present the useful infomation from different sources in a concise and practical way.

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